1. Field of the Invention
The invention relates to a process flow for preparing DRAM cells with collar isolation layers for about 45 degrees rotated trench cells with narrow spaces between bottles, thereby avoiding the space required by a final collar (that may include collar RIE processing). More particularly, the invention process includes etching a trench, forming a sacrificial collar to make a thin nitride layer in the top part of the trench, and etching the bottle shape formation in the trench.
2. Description of the Prior Art
U.S. Pat. No. 6,326,261 disclose a method of fabricating a deep trench capacitor. After several process steps, including formation of a deep trench 38, a silicon nitride layer 40 is deposited on the substrate 32. Subsequently, a photoresist layer 42 fills in the deep trench 38, with the surface of the photoresist layer 42 aligned with the tops of the deep trench 38. Therein, the silicon nitride layer 40 uniformly covers both the surfaces of the pad stack 34 and the deep trench 38. Following the baking of the photoresist solution, an oxygen plasma is used to etch back the baked photoresist to form a photoresist layer 42 of an appropriate thickness. A wet etching is performed, to remove the silicon nitride layer 40 not covered by the photoresist layer 42 and to expose the substrate 32 in the upper region of the deep trench 38. After the removal of the photoresist layer 42, a high-temperature oxidation process, such as a rapid thermal process operated under a moist environment, is performed to simultaneously grow a first oxide film (not shown) on the surface of the silicon nitride layer 40 and a second oxide film on the exposed substrate 32 in the upper region 43 of the deep trench 38. The second oxide film, also called a collar oxide 46, is formed to reduce parasitic leakage from the deep trench 38. (FIGS. 8-10; col. 3, line 40, col. 4, line 9).
A low-resistance salicide fill for trench capacitors is disclosed in U.S. Pat. No. 6,194,755. FIG. 1(a) shows a cross-sectional view of an initial bottle-shaped trench structure 10. Narrow upper region 16a preferably contains an oxide collar 22 which may be formed by local oxidation of silicon (LOCOS) (col. 3, lines 18-20).
U.S. Pat. No. 6,025,245 disclose a method of forming a trench capacitor with a sacrificial silicon nitrate sidewall. A silicon nitride layer 202 is formed on the silicon substrate 201. A thick oxide layer 203 is then formed and patterned on the silicon nitride layer 202 to define a deep trench region. The thick oxide layer 203 is then removed. A tetraethyl-orthosilicate (TEOS) oxide layer 204 is formed in the deep trench region 200 and on the silicon nitride layer 202. The TEOS oxide layer 204 is recess etched. In this etching, a portion of silicon substrate 201 is exposed in the deep trench region 200 to form a trench sidewall. A thermal oxidation is performed to form a collar oxide 205 on the exposed silicon substrate 201. (FIGS. 2-4; col. 3, lines 5-46).
A method of forming a hemispherical grained capacitor is disclosed in U.S. Pat. No. 6,159,874. After several process steps, including formation of a trench 22, a thin silicon dioxide layer 24 is next grown on walls 23 of trench 22 to passivate and protect walls 23. Next, a silicon nitride layer 26 is deposited over silicon dioxide layer 24, and etched using conventional photolithographic chemical etching techniques such that silicon nitride layer 26 covers only a lower portion 28 of trench 22. An upper portion 30 of trench 22 remains uncovered by silicon nitride layer 26. A localized oxidation of silicon (LOCOS) collar 32 is next formed in upper portion 30 of trench 22 by a conventional LOCOS process, here thermal oxidation of silicon substrate 10 surrounding upper portion 30 of trench 22. (FIGS. 2C-2E; col. 3, lines 29-48).
U.S. Pat. No. 5,656,535 disclose a storage node process for deep trench-based DRAMS. After several process steps, including formation of a trench 18. A node reoxidation process oxidizes the node dielectric 20 remaining in the deep trench 18 and grows a collar oxide 24. The node reoxidation process uses a thermal wet oxidation to grow the collar oxide 24 along the deep trench sidewall 19 to a thickness of approximately 50 nm. (FIGS. 4 and 5; col. 3, lines 37-45).
A method for forming trench capacitors in an integrated circuit is disclosed in U.S. Pat. No. 6,008,103. After the trench is etched, the trench interior is coated with a suitable liner layer 704 (e.g., a nitride layer). The liner layer is etched back using a photoresist plug process so that the remaining nitride liner at least covers the region within the trench where the buried plate will eventually be formed. A suitable photoresist plug process to facilitate the liner etch may involve filling the trench with photoresist (706 in FIG. 7A) and then etching the photoresist back within the trench to about the level of the top of the future buried plate to form a photoresist plug therein (706A in FIG. 7B). Thereafter, a liner etch process is performed to remove the liner material within the trench that is not covered by the photoresist plug. The liner material that is protected by the photoresist plug at the bottom of the trench remains substantially unattacked during the liner etch process. The unetched liner layer is shown in FIG. 7B as liner layer 704A. Thereafter, the photoresist plug itself may be removed, leaving behind a liner coating that covers the portion of the trench interior up to the level of the (now removed) photoresist plug. The silicon region in the trench where the collar is to be formed (region 710 FIG. 7B) is not covered by the liner material. Accordingly, the silicon material in region 710 of FIG. 7B is subsequently oxidized in an oxidization step to form the oxide collar (using, for example, either a wet or dry oxidation process). (FIGS. 7A-7C; col. 5, line 12-col. 6, line 41).
There is a need in the art of forming DRAM cells, in which a metal oxide semiconductor (MOS) transistor is connected to a capacitor to devise a process scheme that isolates the top trench with vertical cell and active area from the buried plate without requiring an additional collar, so that, in the top trench, the trench diameter is equal to the design measure, thereby allowing for maximum silicon thickness in the active area and for improved body contact, and so that, due to the absence of a final collar layer, the trench can be filled with maximum thickness of trench fill, e.g. poly silicon.
It is therefore an objective of the present invention to provide a process flow for DRAM cells that isolates the top trench with vertical cell and active area from the buried plate, so that no additional collar is required, and so that, in the trench top, the trench diameter is equal to the design measure, thereby allowing for maximum silicon thickness in the active area and for improved body contact, and so that, due to the absence of a final collar layer, the trench can be filled with the maximum thickness of trench fill, e.g. poly silicon, and to allow resistance of the trench fill to be optimized.
In a preferred embodiment, the present invention process provides a process flow from DRAM cells with collar isolation layers by:
a) etching a deep trench (DT) in a substrate over which a patterned pad stack is positioned, said patterned pad stack serving as a mask;
b) depositing a silicon nitride sacrificial collar layer or liner in a top part of the trench;
c) affecting an etch below the sacrificial collar to form a bottle-shaped structure in a lower part of the trench;
d) forming an oxide layer, forming a nitride layer over the oxide layer, depositing a resist fill, and affecting a recess of the resist fill so that the resist recess depth is below the top of the bottle formation;
e) affecting a nitride etch followed by a resist strip;
f) affecting a thermal oxidation using the nitride layer as a mask to form a closed layer of oxide at the top of the trench bottle-shaped structure;
g) affecting a nitride strip; and
h) affecting a gas phase doping (GPD) to form a buried plate so that the closed layer causes isolation between the active area and the buried plate.
Alternatively, between steps e) and f) P well buried plate doping may be affected using gas phase doping.